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PIC32MX3XX/4XX
7.0
INTERRUPT CONTROLLER
PIC32MX3XX/4XX devices generate interrupt requests
in response to interrupt events from peripheral mod-
Note 1: This data sheet summarizes the features
of the PIC32MX3XX/4XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 8. “Interrupt
Controller” (DS61108) of the “PIC32MX
Family Reference Manual” , which is
ules. The Interrupt Control module exists externally to
the CPU logic and prioritizes the interrupt events before
presenting them to the CPU.
The PIC32MX3XX/4XX interrupts module includes the
following features:
? Up to 96 interrupt sources
? Up to 64 interrupt vectors
available from the Microchip web site
(www.microchip.com/PIC32).
2: Some registers and associated bits
described in this section may not be avail-
“Memory Organization” in this data
sheet for device-specific register and bit
information.
?
?
?
?
?
?
?
?
?
?
Single and Multi-Vector mode operations
Five external interrupts with edge polarity control
Interrupt proximity timer
Module Freeze in Debug mode
Seven user-selectable priority levels for each
vector
Four user-selectable subpriority levels within each
priority
Dedicated shadow set for highest priority level
Software can generate any interrupt
User-configurable interrupt vector table location
User-configurable interrupt vector spacing
FIGURE 7-1:
INTERRUPT CONTROLLER MODULE
Vector Number
Interrupt Controller
Priority Level
Shadow Set Number
CPU Core
Note:
Several of the registers cited in this section are not in the interrupt controller module. These registers (and
To avoid confusion, a typographic distinction is made for registers in the CPU. The register names in this
section, and all other sections of this manual, are signified by uppercase letters only. The CPU register
names are signified by upper and lowercase letters. For example, INTSTAT is an Interrupts register;
whereas, IntCtl is a CPU register.
? 2010 Microchip Technology Inc.
DS61143G-page 89
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